module mux_RegDst(a1,a0,rw,RegDst);
  	input[4:0]a1,a0; //rd,rt
  	input RegDst;
  	output reg[4:0]rw;

	always@(*)begin
  		if(RegDst)
			rw=a1;  //1 -> rd [15:11]
  		else 
			rw=a0;  //0 -> rt [20:16]
  	end

endmodule
